Useful clock skew optimization under a multi-corner multi-mode design framework

Weixiang Shen1,  Yici Cai1,  Wei Chen2,  Yongqiang Lu1,  Qiang Zhou1,  Jiang Hu3
1EDA Lab, Dept. of Computer Science and Technology, Tsinghua University, Beijing, 100084, China, 2Magma Design Automation Inc., 1650 Technology Drive, San Jose, CA 95110, USA, 3Dept. of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843-3228, USA


As VLSI technology scales into sub-65nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode design, some more efficient methods need to be invented. In this work, we propose to address such a kind of issue by exploiting useful clock skew, which can help reduce timing violations rapidly. We also add mode/corner metric balancing measurements to make this method more flexible and applicable especially in such deep stages while the CTS is ready. The results indicate that our method can achieve an average improvements of 33.16% on the worst slack (WS) and 75.56% on the total negative slack (TNS), respectively.