Simultaneous Extraction of Effective Gate Length and Low-field Mobility in Non-uniform Devices

Vivek Joshi1,  Kanak Agarwal2,  Dennis Sylvester1
1University of Michigan, 2IBM Research Austin


Advanced semiconductor technologies use mechanical stress to enhance carrier mobility and achieve higher performance. Layout dependence of induced stress causes the stress profile, and hence the carrier mobility along the device channel, to vary across device width. Additionally, sub-wavelength lithography causes printed shapes to deviate from drawn rectilinear shapes, resulting in non rectangular gates (NRG). In this work, we present a novel method to effectively model non rectangular gates with non uniform carrier mobility. First, we propose a slicing and summing based approach to calculate effective carrier mobility for a device. We then develop a methodology for simultaneous extraction of effective gate length (EGL), and effective carrier mobility (ECM), to enable accurate prediction of both device drive current and leakage. We show that this method is much more accurate than previously proposed approaches which neglect the mobility variation across device width, as well as independent calculation of EGL and ECM. Experimental results show that independent calculation of EGL and ECM results in errors of up to 4.1% and 38.2% (as compared to simultaneous calculation), in the device drive current and leakage, respectively. Gate level results show an average error of 4.7% in average delay, and 34.2% in average leakage.