Novel Low-Power 12-bit SAR ADC Architecture for RFID Tags

Daniela De Venuto1,  Eduard Stikvoort2,  Youri Ponomarev3,  David Castro3
1Politecnico di Bari - Italy, 2Eindhoven, Netherland, 3NXP Leuven, Belgium


The design and first measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for the lowest power consumption. The proposed design has a power consumption of 0.52µW at a bitclock of 50-kHz and of 0.85µW at 100-kHz with a 1.2-V supply. As far as we know, the Figure-of-Merit of 66 fJ/convertion-step is the best reported so far. The ADC was realised in the NXP CMOS 0.14µm technology with an area of 0.35 mm^2. Only four metal layers were used in order to allow 3D integration of the sensors.