Process Variation Tolerant On-Chip Communication Using Receiver and Driver Reconfiguration

Ethiopia Nigussie,  Juha Plosila,  Jouni Isoaho
University of Turku


We present a process variation tolerance technique for current sensing on-chip links. Process variation affects the signal integrity of a current sensing receiver. The conventional assumption of worst-case process variation has a high power consumption cost as the amount of worst-case current variation is increasing in sub-100nm technologies. We propose adjusting currents at every power start-up of the system through receiver and driver reconfiguration when an error is detected due to the current variation. This makes the link adaptive to the effect of variations enabling continuous and reliable operation of the link. It also results in lower power consumption than worst-case approach. An error detection scheme as well as a reconfiguration algorithm and methodology are developed. Furthermore, reconfiguration control and communication circuits are designed and simulated for a multilevel current sensing link. Depending on the detected error(s), the time it takes to adjust the currents and start the normal data transmission phase ranges from 2.66ns to 5.72ns. The proposed technique is area efficient for relatively wide links. For a 64-bit link the overhead is 4.67% silicon area and 2.63% wiring area. The circuits are designed and simulated in Cadence Analog Spectre using 65nm CMOS technology from STMicroelectronics.