Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration

Hiroaki Konoura,  Yukio Mitsuyama,  Masanori Hashimoto,  Takao Onoye
Osaka University


NBTI degradation proceeds while a negative bias is applied to the gate of PMOS, whereas, it recovers while a positive bias is applied. Therefore, PMOS stress (ON) probability has a strong impact on the prediction of circuit timing degradation due to NBTI effect. This paper evaluates how the granularity of stress probability calculation affects NBTI prediction using the state-of-the-art long term prediction model. Experimental results show that the prediction accuracy of timing degradation due to NBTI effect is heavily dependent on granularity of stress probability consideration in timing analysis.