A Yield Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule

Masanori Kurimoto,  Jun Matsushima,  Shigeki Ohbayashi,  Yoshiaki Fukui,  Michio Komoda,  Nobuhiro Tsuda
Renesas Technology Corp.


We propose a yield improvement methodology which repairs a faulty chip due to the logic defect by using a repairable scan flip-flop (R-SFF). Our methodology improves an area penalty, which is a large issue for the logic repair technology in the actual products, greatly by using a repair grouping and a redundant cell insertion algorithm, and by pushing the design rule for the repairable area of R-SFF. Besides, we reduce the number of wire connections around the redundant cell compared with the conventional method by improving the replacement method of the faulty cell. The proposed methodology reduces total area penalty by the logic redundant repair to 3.6%, and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[cm-2].