A Novel All Digital Fractional-N Frequency Synthesizer Architecture with Fast Acquisition and Low Spur

Jun Zhao and Yong-Bin Kim
Northeastern University


Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthesizers suffer form the fractional spur due to the application of fractional divider. A new architecture of an all digital fractional-N phase-locked loop based frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is application of an extra time-to-digital converter (TDC) to measure the fractional value. The proposed Fraction-N frequency synthesizer is implemented using 32nm CMOS Predictive Technology Model (PTM) at 0.9V supply voltage. In the implementation example, input reference frequency is 300 MHz, frequency division factor is 2.125. The proposed circuit architecture accomplishes fast acquisition (6 cycles) time and low spurs levels.