Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study

Syed M. A. H. Jafri1,  Stanislaw J. Piestrak2,  Olivier Sentieys3,  Sebastien Pillement3
1University of Rennes 1, 22300 Lannion, France, 2IRISA/INRIA---University of Rennes 1, 22300 Lannion, France, 3IRISA/INRIA---University of Rennes 1,22300 Lannion, France


This paper considers the possibility of implementing low-cost hardware techniques which would allow to tolerate temporary faults in the datapaths of coarse-grained reconfigurable architectures (CGRAs). Our goal was to use less hardware overhead than commonly used duplication or triplication methods. The proposed technique relies on concurrent error detection by using residue code modulo 3 and re-execution of the last operation, once an error is detected. We have chosen the DART architecture as a vehicle to study the efficiency of this approach to protect its datapaths. Simulation results have confirmed hardware savings of the proposed approach over duplication.