A 2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead

Jawar Singh1,  D.S. Aswar2,  Dhiraj Pradhan1,  S.P. Mohanty3
1University of Bristol, UK, 2, 3University of North Texas, USA


Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we present a 2-port 6T SRAM bitcell with multi-port capabilities and a reduced area overhead compared to existing 2-port 7-transistor (7T) and 8T SRAM bitcells. The proposed 2-port bitcell has six transistors (6T) and single-ended read and write bitlines (RBL/WBL). We compare the stability, simultaneous read/write disturbance, SNM sensitivity and misread current from the read bitline with the 7T and 8T bitcells. The static noise margin (SNM) of the 6T bitcells around the write disturbed bitcell is 53% to 61% higher than that of the 7T bitcell. The average active power dissipation under the different read/write operations of the 6T bitcells is 28% lower than the 8T and equal to 7T bitcell. Hence, the proposed 2-port 6T-SRAM is a potential candidate in terms of process variability, stability, area, and power dissipation.