Methodology From Chaos in IC Implementation

Kwangok Jeong and Andrew Kahng
University of California San Diego


Algorithms and tools used for IC implementation do not show deterministic and predictable behaviors with input parameter changes. Due to suboptimality and inaccuracy of underlying heuristics and models in EDA tools, overdesign using tighter constraints does not always result in better final design quality. Moreover, negligibly small input parameter changes can result in substantially different design outcomes. In this paper, we assess the nature of ‘chaotic’ behavior in IC implementation tools via experimental analyses, and we determine a methodology to exploit such behavior based on the ‘multi-run’ and ‘multi-start’ sampling concepts proposed in [2]. We also suggest the number of sampling trials that yields more predictably good solutions; this allows us to improve quality of design without any manual analysis or manipulation, without changing any existing tool flows, and without unnecessary expenditure of valuable computing resources.