A Robust and Low Power Dual Data Rate (DDR) Flip-Flop Using C-Elements

Srikanth Devarapalli1,  Payman Zarkesh-Ha1,  Steven Suddarth2
1University of New Mexico, 2COSMIAC


To maintain the performance of digital systems, while reducing the energy consumption, implementation of dual edge flip flops has recently become the focus of many researchers. This paper presents a new robust and low power dual edge flip-flop suing c-elements. Unlike the existing dual data rate (DDR) flip flops [1-4], the proposed circuit uses the direct clock pulses to latch the data, without a need for additional pulse generator circuitry for the clock signal, which lower the clock dynamic power consumption by factor of 2x. Moreover, because of its simplicity and minimum number of transistors used in this design, it provides a more robust solution for DDR flip-flops.

In comparison with ep-DSFF (explicit-pulsed static hybrid flop) [1] at 45nm CMOS process, the proposed DDR-FF consumes 32% less power, with 21% less C2Q delay. The power-delay product of the proposed DDR-FF is 46% better than its counterpart, ep-DSFF. The proposed DDR-FF uses only 24 transistors and can easily be implemented into the cell libraries for high performance and low power ASIC design flow.