A Low Power Charge-Redistribution ADC With Reduced Capacitor Array

Mallik Kandala,  Ram Gopal Sekar,  Chenglong Zhang,  Haibo Wang
Southern Illinois University Carbondale


This paper presents a novel low power charge redistribu- tion successive approximation analog to digital converter(CR- SAR ADC). During its conversion, the capcitor array volt- age swing is reduced to half of the voltage reference without decreasing the A/D converter dynamic range. The reduced voltage swing results in a significant reduction on the A/D converter power consumption. Also, the proposed design re- quires only half of the total capacitance compared to tradi- tional CR-SAR ADC. The power consumption due to charg- ing the capacitor array in the proposed design is compared with that of previous low-power charge redistributed A/D converters based on analytical power estimation equations and Matlab simulation. The proposed circuit is implemeted using a 0.13μ CMOS technology . Post-layout simulation shows that the proposed converter consumes more than 60% less energy compared to traditional CR-SAR ADC