Layout-Aware Illinois Scan Design for High Fault Coverage

Shibaji Banerjee1,  Jimson mathew1,  Dhiraj Pradhan1,  Saraju P Mohanty2
1University of Bristol, 2Univ of North Texas, Denton, TX 76203


The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume required to test today’s high density VLSI circuits. However, to achieve high fault coverage with ILS architecture one requires judicious grouping and ordering of scan flip-flops for selecting these segments. This may also increase the wiring complexity and cost of the scan chain, as the physical locations of the flip-flops on silicon are determined at an early design stage before scan insertion. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. This consequently, reduces the number of test patterns required in serial mode. The proposed methodology reduces test application time significantly, and at the same time, achieves high fault coverage. Experimental results on various benchmark circuits demonstrate the efficacy and versatility of the proposed method.