Design of Low-Power Variation Tolerant Signal Processing Systems with Adaptive Finite Word-length Configuration

Yang Liu1,  Jibang Liu2,  Tong Zhang2
1Juniper Networks, 2Rensselaer Polytechnic Institute


This paper concerns the design of low power digital signal processing integrated circuits in the presence of significant process variations. The basic idea is to leave smaller-than-worst-case timing margin for improving energy efficiency during the design phase and selectively reduce the finite word-length of circuit datapaths in post-silicon to eliminate all the timing faults during the run time. This simple idea can be intuitively justified by the fact that process variations may render only a few post-silicon datapaths to timing faults, while reducing the finite word-length of a few datapaths in signal processing systems may not necessarily make the overall algorithm-level performance unacceptable in run time. We present a design flow to implement this method and propose a dual finite word-length configuration strategy to simplify its real-life realization. Using linear low-pass filter and Turbo code decoder design at 45nm node as case studies, we quantitatively demonstrate that this adaptive finite word-length configuration design strategy may effectively relax the timing margin and accordingly reduce the power consumption by over 18% over conventional worst-case design approach.