Low Power Clock Gates Optimization For Clock Tree Distribution

Siong Kiong Teng1 and Dr Norhayati Soin2
1Penang Design Center, Intel Microelectronics, Penang, Malaysia, 2Dept. of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia


Clock gating techniques had become one of major dynamic power saving approach in today low power digital circuit design. In this paper, we present a new physical clock gates optimization technique using splitting and merging algorithm that works on both single level and multiple levels clock gating design. The algorithm build on top of standard EDA flow by running two passes clock tree synthesis. The first pass is to obtain the clock buffer location for clock gate swapping and the second pass will build the clock tree based on the optimum clock gate location. The merging algorithm will then be used to improve the overall clock tree power. The results on the industrial design show the improvement on overall clock tree power using aforementioned algorithm. The paper presented the new approach of optimization clock tree power.