Clock Buffer Polarity Assignment Considering the Effect of Delay Variations

Minseok Kang and Taewhan Kim
Seoul National University


This work completes the task of polarity assignment by including the satisfaction of yield constraint under delay variations. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial delay correlations, and the clock skew and yield constraints, we solve the problem of assigning polarity to each sink buffer (i.e., assigning a buffering type) so that the power/ground noise is minimized while satisfying the yield and clock skew constraints. Specifically, we solve the problem in two steps where in step 1, for each pair of sinks a set of feasible combination(s) of polarities to the sinks that do not violate the yield constraint as well as the clock skew constraint is extracted, and in step 2, a stepwise greedy method is applied to determine the polarities to sinks from the feasible sets obtained in step 1 to minimize the power/ground noise.