Automatic Generation of Saturation Constraints and Performance Expressions for Geometric Programming based Analog Circuit Sizing

Supriyo Maji,  Samiran Dam,  Pradip Mandal
Indian Institute of Technology, Kharagpur


This paper presents a new approach for generating saturation constraints and dc performance expressions for analog integrated circuits. It also proposes a generalized method to develop ac performance expressions of the same in posynomial form. The developed posynomial expressions can be used for well established geometric programming (GP) based sizing optimization. The equation generation method takes very less time and does not require any manual intervention. The proposed method for ac performance expression generation is built on two levels of abstraction of the circuit. At the higher level, referred as macromodel, circuit performance metrics are modeled as function of device parameters such as transconductance (gm), drain conductance (gd) and overdrive voltage (vov). Whereas, at lower level of abstraction, the device parameters are monomial functions of device sizes and their biases. The two levels abstraction help to develop technology independent performance model of a circuit whereas, the technology dependency is captured through device models. The proposed methods are applied to two well-known CMOS op-amp topologies namely, two-stage and folded-cascode to generate saturation constraints, dc and ac performance expressions. With the developed constraints, both the circuits are designed through GP based circuit optimization in a 0.18m UMC technology. Performance of both are verified at their final design points.