Crosstalk Aware Coupled Line Delay Tree Construction for On-chip Interconnects

Tuhina Samanta1,  Sanoara Khatun1,  Hafizur Rahaman1,  Parthasarathi Dasgupta2
1Bengal Engineering and Science University, Shibpur, 2Indian Institute of Management, Calcutta, India


Crosstalk noise dominates in deep submicron VLSI design as interconnects are more closely placed over a small layout area. Signal response and signal integrity is largely affected by crosstalk delay and noise. In this paper, we propose a coupled line delay model for on-chip interconnects during global routing, with crosstalk between wires as the parameter to be optimized. Our proposed model is influenced by moment matching model of a transmission line. We propose an algorithm for crosstalk aware delay tree construction, optimizing the effect of crosstalk delay in the tree structure by employing a cut − and − join strategy. Experiments are done on some benchmark instances, and for varying technology parameters. Simulation results obtained are quite encouraging.