Block-Basis On-Line BIST Architecture for Embedded SRAM Using Wordline and Bitcell Voltage Optimal Control

Masahiro Yoshikawa,  Shunsuke Okumura,  Yohei Nakata,  Yuki Kagiyama,  Hiroshi Kawaguchi,  Masahiko Yoshimoto
Kobe University


System-on-chip (SOC) is getting smaller and denser. Shrinking transistor size facilitates the integration of functionality on the chip operating at low supply voltage, whereas this trend lowers reliability of a silicon chip. It is, however, needed to keep complete functionality during long duration, even under changing environments such as temperature fluctuation and/or device wearout: Bias temperature instability has to be considered as a time-varying parameter as well. Thus, techniques, which can keep the chip reliable with self-diagnosis and self-repair capabilities, are required. In this paper, we propose a dependable SRAM with built-in self-test that can diagnose and repair itself using wordline and bitcell voltage control. The proposed SRAM consists of memory blocks, and each block has the independent supply voltages for the wordlines and bitcells. This diagnosis and repair scheme is especially effective for a fault that occurs in the field. The self-testing capability is available on-line and completely transparent to a user, who can use the SRAM without any modification or speed degradation in the memory access protocol. A 1-Mb (64-Kb x 16 blocks) SRAM with the BIST was fabricated with a 65-nm CMOS process and verified. The area overhead is 2.8%.