A Design Time Simulator for Computer Architects

Sangeetha Sudhakrishnan1,  Francisco J. Mesa Martinez2,  Jose Renau2
1University of California, Santa Cruz, 2Univeristy of California, Santa Cruz


Processor design and implementation is a very complex and resource intensive enterprise. In an ideal situation, designers should quantify the design time implications of their architectural proposals but in reality they do not have such capacity. To address the lack of quantitative methodologies to estimate processor design time, this paper introduces a new class of event-driven simulation: udsim.

Our proposed simulation infrastructure models the interaction between engineers during the development and verification cycles.To validate udsim, we compare estimated design times against data gathered during the development and verification of three different academic processors and three industrial multiprocessor systems. As an example application for the architectural community, we estimate the design time for a previously published architectural proposal.