Soft Error Reduction through Gate Input Dependent Weighted Sizing in Combinational Circuits

Warin Sootkaneung and Kewal K Saluja
Department of Electrical and Computer Engineering, University of Wisconsin-Madison


As technology nodes are gradually shrinking, adding soft error tolerant features to logic circuits is becoming a challenging task that requires careful consideration. Careless use of sizing technique may even worsen immunity to soft errors for circuits with very small nodes. This paper investigates limitations of conventional sizing methods and introduces new techniques for mitigating soft errors in nanometer circuits. Our techniques employ two algorithms. The first algorithm is called soft error rate saturation consideration algorithm. This algorithm prevents a gate from being oversized and thus, it limits the soft error rate of the circuit. The second algorithm, called weighted area distribution algorithm, can fairly distribute area overhead to the most sensitive gates. In order to assess our work, we compare the yields from different upsizing scenarios and the experimental results show that the sizing based approach that includes both proposed algorithms provides the largest soft error rate reduction.