Three-dimensional integration has the potential to increase integration density and to reduce communication latency of chip-multiprocessors (CMPs). However, the high power density (i.e., power dissipation per unit volume) due to the high integration incurs temperature-related problems in reliability, power consumption, performance, and system cooling cost. In this paper, we propose a design-time solution for temperature-constrained multi-core systems with 3D stacked cache memory in order to maximize the instruction throughput. The proposed method combines the power gating of 3D stacked cache memory, which adapts cache partitioning , and dynamic voltage and frequency scaling (DVFS) of CMP in a temperature-aware manner. Experimental results show that the proposed method offers up to 32 % (average 15%) performance improvement in terms of instructions per second (IPS) compared with an existing method which only performs cache partitioning without temperature consideration.