Lithography-Aware Layout Modification Considering Performance Impact

Hongbo Zhang1,  Yuelin Du1,  Martin D. F. Wong1,  Kai-Yuan Chao2
1Dept. of ECE, UIUC, 2Intel Corporation


As regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research. In 1-D design, line-end gaps are the main sources of printing difficulties. Recently, we [4] demonstrated that printability can significantly improved by intelligently (litho-aware) changing the gap distribution using techniques such as line-end extension and dummy insertion. Note that gate redistribution techniques require layout modification of the original layout and thus will have impact on circuit performance and power consumption. Such potentially undesirable impacts on performance and power were not considered in [4] and deserve a careful investigation which is the subject of our study. In this paper, we present performance-driven gate redistribution algorithms which consider bounds on line-end extension. Experimental results demonstrate the feasibility of our algorithms, and lithography simulation and circuit analysis show the trend of the tradeoff between printability, delay, and power.