A 128kb High Density Portless SRAM Using 
Hierarchical Bitlines and Thyristor Sense Amplifiers

Michael Wieckowski,  Gregory Chen,  Daeyeon Kim,  Dennis Sylvester,  David Blaauw
University of Michigan


A 128 kb portless SRAM is presented with 1024 rows per hierarchical bitline and CMOS thyristor-based local sense amplifiers. Each portless cell is 0.317 μm2 in 45nm CMOS and consumes 50.8 fJ of energy per access at a 17.86 ns cycle time. A 65% read SNM improvement and a 33% leakage power reduction is achieved over a conventional 6T design. The thyristor-based sense amplifier occupies 2.4 μm2 and provides variation tolerant sensing within the hierarchical column pitch.