BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits

Mahesh Poolakkaparambil1,  Jimson Mathew2,  Abusaleh Jabir1,  Dhiraj Pradhan2,  Saraju Mohanty3
1Oxford Brookes University, 2University of Bristol, 3University of North Texas


This paper introduces a design methodology for multiple bit error detection and correction in Galois filed arithmetic circuits such as the bit parallel polynomial basis (PB) multipliers over GF(2^m). These multipliers are crucial in most of the cryptographic hardware and hence we must ensure that they are not vulnerable to security threats. Security threats arising from injected soft (transient) faults into a cryptographic circuit can expose the secret information, e.g. the secret key, to an attacker. To prevent such soft or transient fault related attacks, we consider fault tolerance as a method of mitigation. Most of the current fault tolerant schemes are only multiple bit error detectable but not multiple bit error correctable. Keeping this in view, we present a multiple bit error correction scheme based on the BCH codes, with a very efficient bit-parallel Chien search module. This paper details the design procedure as well as the hardware implementation specs. Comparison with existing methods demonstrate improved area and reduced delay performances.