On Evaluating Signal Selection Algorithms for Post-Silicon Debug

Eddie Hung and Steven J. E. Wilton
University of British Columbia


Post-silicon debug is becoming an increasingly important part of the integrated circuit design flow. The cost and time required to validate a fabricated chip has motivated many designers to include trace buffers in their designs to record the value of key signals during chip operation. The effectiveness of these trace buffers depends on the signals selected for observation. In this paper, we present a metric to evaluate the effectiveness of such post silicon debug solutions; this metric quantifies the expected number of system states that can be "ruled out" by observing this set of signals. We apply our metric on a previous signal selection technique which aims to minimize the state space of the circuit indirectly by reconstructing additional signals, and compare this to our own algorithm which directly minimizes this objective.