Statistical Full-Chip Dynamic Power Estimation Considering Spatial Correlations

Zhigang Hao1,  Ruijing Shen2,  Sheldon X.-D. Tan2,  Bao Liu3,  Guoyong Shi1,  Yici Cai4
1Shanghai Jiao Tong University, 2University of California, Riverside, 3University of Texas at San Antonio, 4Tsinghua University


Estimating the dynamic powers is crucial for power and energy efficient chip designs. With increasing variability from manufacture processes, dynamic powers can manifest significant variations due to uncertainties in device geometry and delay variations. In this paper, we propose a new statistical dynamic power estimation method considering the spatial correlation in process variation. We first show that channel length variation have significant impacts on the dynamic power of a gate. To consider the spatial correlation of channel length variation, we adopt a newly proposed spatial correlation model where a new set of uncorrelated variables are defined over virtual grids to represent the original physical random variables by least-square fitting. To compute the statistical dynamic power of a gate on the new set of variables, the new method applies the orthogonal polynomials based method. We use the segment-based statistical power method to consider impacts of the glitch variations on dynamic powers. The orthogonal polynomial of a statistical gate power is computed based on switching segment probabilities. The total full chip dynamic power expressions are then computed by summing up resulting orthogonal polynomials (their coefficients). Experimental results show that the proposed method has about $300X$ speedup over recently proposed statistical dynamic power analysis method and many orders of magnitudes over the Monte Carlo method.