An Efficient Statistical Chip-Level Total Power Estimation Method Considering Process Variations with Spatial Correlation

Zhigang Hao1,  Sheldon X.-D. Tan2,  Guoyong Shi1
1Shanghai Jiao Tong University, 2University of California, Riverside


In this paper, we proposed an efficient statistical chip-level total power estimation method considering process variations with spatial correlation. Instead of computing dynamic power and leakage power separately, the new method compute the total power via circuit level simulation under realistic input testing vectors. To consider the process variations with spatial correlation, we first apply principle factor analysis method (PFA) to transform the correlated variables into uncorrelated ones and meanwhile reduce the number of resulting random variables. Afterwards, Hermite polynomials and sparse grid techniques are used to estimating total power distribution in a sampling way. The proposed method has no restrictions on models of statistical distributions for total powers. The proposed method works well when strong spatial correlation exists among random variables in the chip. Experimental results show that the proposed method has $78X$ times speedup than the Monte Carlo method under fixed input vector and $26X$ times speedup than the Monte Carlo method considering both random input vectors and process variations with spatial correlation.