Intentional skew is known to be useful for improving clock frequency and/or tolerance to delay variations. This paper proposes a complete framework for treating skew schedule in the high level datapath synthesis. Major contributions include (1) the incorporation of timing issue on multiplexer-control into the skew scheduling problem (previously, only timing issue on register-control has been discussed, but it is incomplete for a datapath circuit which is controlled by control-signals to registers and multiplexers), and (2) a complete MILP (Mixed Integer Linear Programming) formulation of simultaneous functional unit (FU) binding and register incorporating with skew scheduling. Experimental examples demonstrate the correctness and the effectiveness of our framework.