SEU Tolerant SRAM Cell

Sudipta Sarkar1,  Anubhav Adak1,  Virendra Singh1,  Kewal Saluja2,  Masahiro Fujita3
1Indian Institute of Science, 2Univ. of Wisconsin-Madison, 3Univ. of Tokyo


Modern integrated circuits require careful attention to the soft errors resulting into bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more severe for future technologies. In this paper we propose a novel 10T SEU tolerant SRAM cell design. Our SRAM cell is area efficient in comparison with the earlier proposals. Simulation results show that the proposed cell is robust as it does not flip even for a transient pulse with four times the Qcrit of a standard 6T SRAM cell.