Layout-aware Mismatch Modeling for CMOS Current Sources with D/A Converter Analysis

Bo Liu,  Qing Dong,  Bo Yang,  Jing Li,  Shigetoshi Nakatake
University of Kitakyushu, Japan


The mismatch of current sources is caused by the circuit error and the process variation. Introducing the channel length modulation to the Pelgrom model for variation analysis, we describe a new current mismatch model of current sources. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90nm process technology, where we can collect the characteristics variation for MOSFETs of various layout structures. The test chip also includes D/A converters to check the differential non-linearity (DNL) caused by the mismatch of current sources when behaving as a DAC. Compared to the variation values by removing the circuit errors from the measured DNLs, we show that our mismatch model with lambda is more accurate than the original Pelgrom model. Furthermore, we reveal the layout dependency in our model for higher accuracy.