Accurate Analysis of Substrate Sensitivity of Active Transistors in an Analog Circuit

Satoshi Takaya1,  Yoji Bando1,  Toru Ohkawa2,  Toshiharu Takaramoto2,  Toshio Yamada2,  Masaaki Souda2,  Shigetaka Kumashiro2,  Tohru Mogami2,  Makoto Nagata1
1Kobe University, 2MIRAI-Selete


A tailored substrate network for a variety of transistor geometry including channel sizes, fingering and folding, and shapes and placements of guard bands, extends the capability and accuracy of full-chip noise coupling analysis of mixed signal VLSI integration. Analysis of substrate sensitivity of differential amplifiers in a 90 nm CMOS technology with more than 64 different geometry and operating conditions well agrees with on-chip noise coupling measurements, with the discrepancy of as low as 3 dB.