Integrated Circuit-Architectural Framework for PSN Aware Floorplanning in Microprocessors

Mandar Padmawar1,  Sanghamitra Roy2,  Koushik Chakraborty2
1AES Corporation, 2Utah State University


With continued scaling of transistor feature size, aggressive use of power saving techniques exacerbates the Power Supply Noise (PSN) problem in high performance microprocessors. PSN in an integrated circuit depends on the the interplay of the intrinsic circuit characteristics and the runtime execution of programs on the circuit. Consequently, accurate estimation of PSN in a microprocessor requires combining architectural level activity information with detailed circuit level power supply network modeling. In this paper, we combine architectural execution characteristics of real workloads with detailed power grid modeling, to create an integrated circuit-architectural framework for PSN estimation. We propose a PSN aware floorplanning algorithm using our circuit-architectural framework to reduce the decoupling capacitance requirement of the chip. We evaluate our algorithm on the high performance Alpha processor and several MCNC benchmarks at the 45nm technology node. Our results show on an average 18.94% improvement in PSN reduction over a recently proposed PSN aware floorplanning technique for microprocessors.