Measuring Within-Die Spatial Variation Profile through Power Supply Current Measurements

Jim Plusquellic1,  Dhruva Acharyya2,  Kanak Agarwal3
1University of New Mexico, 2Verigy, 3IBM


Spatial variation in process parameters can have a significant impact on parametric yield of integrated circuits. We present a structure and measurement technique for statistical characterization of process variation with programmable spatial granularity. The proposed structure can measure spatial variation at a desired level of granularity by controlling the leakage and on-current state in different spatial regions through input vectors and measuring the corresponding quiescent (IDDQ) currents at power supply ports. This minimally invasive variation measurement approach can be extended to measure spatial variation profile in actual product chips by leveraging the existing power delivery architecture and power control circuits such as voltage islands and power gating. Measurements on a testchip fabricated in a 65 nm process show nearly a 100% leakage variation and 7% on-current variation over a 558 µm by 380 µm silicon area with nearly 3X leakage variation chip-to-chip.