Multi-Objective Optimization Techniques for VLSI Circuits

Fatemeh Kashfi,  Safar Hatami,  Massoud Pedram
University of Southern California


The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to technology mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex modeling. Next, a class of robust and scalable solution methods for multi-objective optimization problem (MOP) in a digital circuit is presented. We discuss the results of a multi-objective (i.e., power dissipation and delay) gate sizing/ transistor sizing optimization algorithm for a circuit to show the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.