0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM

Hiroki Noguchi1,  Shunsuke Okumura1,  Tomoya Takagi1,  Koji Kugata1,  Masahiko Yoshimoto2,  Hiroshi Kawaguchi1
1Kobe University, 2Kobe University, JST CREST


This paper proposes a novel dependable SRAM with 9T/18T memory cells. The memory cell has a set of additional bitlines (BLs) for read operation compared to the conventional 7T/14T hybrid SRAM cell. Because the cell structure based on dual-port scheme, a stored data can be read through internal BLs and external read BLs, independently and simultaneously. The proposed SRAM has two modes: a normal mode (9T) and a dependable mode (18T), and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information. Additional read port connects two type of readout circuits, a single-end readout inverter circuit and a differential sense amplifier circuit. Additional read port can operate without care of static noise margin because the read margin is free. Thus, 9T/18T SRAM is more stable than 7T/14T SRAM under the effect of the threshold-voltage (Vth) variation. We fabricated the proposed SRAM using 65-nm process and the measurement results show that the dependable read mode using additional read-port can suppress Vth variation affects, and reduce the operation voltage to 0.45 V at a frequency of 1 MHz, while the dependable read mode using internal BLs needs 0.54 V at the same frequency.