Design of Ultra-low-leakage Logic Gates and Flip-flops in High-performance FinFET Technology (Invited)

Ajay Bhoj and Niraj Jha
Princeton University


With the advent of multi-gate CMOS devices like FinFETs, it is essential to redesign/optimize circuit topologies of basic digital elements, by leveraging the advantages offered by mixing shorted-gate (SG) and independent-gate (IG) FinFETs. In this paper, we address the above problem by exploring the design space of FinFET static/dynamic CMOS-style logic gates and sequential elements like latches and flip-flops for trade-offs in leakage-delay, transfer characteristics, dynamic power dissipation, and temperature behavior, using detailed mixed-mode Sentaurus TCAD device simulations. We also characterize the effects of process variations and temperature on leakage power for each topology.