Process Mismatch Analysis based on Reduced-Order Models

Mustafa B Yelten,  Paul D Franzon,  Michael B Steer
North Carolina State University


This paper describes a methodology based on reduced-order models to investigate the effects of process mismatch in analog circuits in the presence of reliability degradation. Neural network-based reduced-order models for the DC drain current, Ids, of 65 nm n- and p-channel transistors have been generated in terms of six process parameters, temperature, and device age. The models identify the contribution of process parameters to the mismatch of n- and p-channel transistors as they age. Hot carrier injection (HCI) is considered as the main reliability degradation for n-channel devices and negative bias temperature instability (NBTI) is considered for p-channel devices. It is demonstrated that the variations of the effective channel length and intrinsic threshold voltage are major contributors to device mismatch in the absence of aging. Finally, a beta multiplier current reference is analyzed using the developed models for the impact of process mismatch with and without the aging effects. Design for manufacturing (DFM) guidelines are proposed.