Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP

Aaron Gower-Hall1,  Tamba Gbondo-Tugbawa1,  JenPin Weng1,  Wei-tsu Tseng2,  Laertis Economikos2,  Toshiaki Yanagisawa2,  Pavan Bashaboina2,  Stephen Greco2
1Cadence Design Systems, 2IBM Semiconductor Research and Development Center


Multi-step Chemical Mechanical Polishing (CMP) has been used in copper interconnect fabrication for more than a decade. During this time, advances in both the CMP-based damascene manufacturing processes, and in the design flows, have enabled significant uniformity improvements for both metal thickness and surface topography, producing corresponding improvements in parametric and functional yields and enabling smaller process nodes. However, improving post CMP planarity and widening CMP process windows have lead to an increased risk of functional yield failures due to copper pooling (sometimes called puddling). These failures occur when the overburden copper or barrier material is not cleared during CMP, producing an electrical short between two neighboring lines.

In this paper we seek to understand the source of this failure mode, based on data trends seen in state of the art copper CMP manufacturing processes. Once copper pooling mechanisms were identified, CMP models were enhanced to more accurately predict pooling hotspot locations. These models can be used to improve CMP process optimization and/or Design for Manufacturing (DFM) based flows that detect and remove pooling hotspots.