Physical-Design-Friendly Hierarchical Logic Built-In Self-Test – A Case Study

Kelvin Nelson1,  Jaga Shanmugavadivelu1,  Jayanth Mekkoth1,  Venkat Ghanta1,  Jun Wu1,  Fe Zhuang1,  Hao-Jan Chao2,  Shianling Wu2,  Jie Rao2,  Lizhen Yu2,  Laung-Terng Wang2
1Cisco Systems, 2SynTest Technologies, Inc.


This paper describes an application of a physical-design-friendly hierarchical logic built-in self-test (BIST) architecture and validation methodology on a networking system-on-chip (SOC) design that consists of two embedded cores, each with approximately 45M primitive instances and 2.5M flip-flops. The implemented architecture supports the at-speed staggered launch-on-capture clocking scheme and includes novel features to yield fast turnaround time during engineering change order (ECO) and reduce the device’s BIST runtime, in addition to facilitating test and diagnosis of the device at the system level. The BIST hierarchy consists of wrappers surrounding each core with access from chip-top allowing for both parallel and serial validations of the cores. This case study successfully demonstrated the feasibility of using the described features for speedy ECO, synergy with physical design flow, and ease of test and diagnosis.