Large dense structures like DRAMs are particularly susceptible to process variation, which can lead to variable latencies in different memory arrays. However, very little work exists on variation studies in the DRAM. This is due to the fact that DRAMs were traditionally placed off-chip and their latency changes due to process variation did not impact the overall processor performance. However, emerging technology trends like three dimensional integration, use of sophisticated memory controllers and continued scaling of technology nodes, substantially reduces DRAM access latency. Hence future technology nodes will see widespread adoption of embedded DRAMs. This makes process variation a critical upcoming challenge in DRAMs that must be addressed in current and forthcoming technology generations. In this paper, we present techniques for modeling the effect of random as well as spatial variation in large DRAM array structures. We use sensitivity based gate level process variation models combined with statistical timing analysis to estimate the impact of process variation on the DRAM performance and leakage power. We also propose a simulated annealing based Vth assignment algorithm using adaptive body biasing to improve the yield of DRAM structures. Applying our algorithm on a 1GB DRAM array, we report an average of 10.3% improvement in the DRAM yield. To the best of our knowledge, ours is the first technique to model the impact of process variation on large scale DRAM arrays.