Device and electromagnetic co-simulation of TSV: substrate noise study and compact modeling of a TSV in a matrix.

Patrick Le Maitre,  Melanie Brocard,  Alexis Farcy,  Jean-Claude Marin


The Wide I/O architecture for mobile application, combining a memory and microprocessor electrically connected by TSV is a good candidate for future memory interfaces. To accurately simulate the signal between the two dice, modeling the TSV in a doped semiconductor is essential.

This paper presents the obtained results from the AC simulation of a TSV, in a via middle process for 28nm node, using a novel simulation tool that enables device and electromagnetic (EM) co-simulation.

The process, the simulation environment and the simulated structures are first presented. A generic structure is composed of a TSV and an active p+ substrate plug. A more specific one, composed of a TSV surrounded by two grounded TSVs, reproduces the TSV-in-matrix situation.The generic structure is simulated at different voltages and frequencies to extract a physics-based TSV model. It provides the oxide and voltage-dependant MOS capacitance, and the silicon equivalent capacitance and conductance. From the specific structure, frequency dependant resistance and inductance are extracted. Electrical impact of the TSVs pitch variations, and distance to substrate plug variations is studied.