Combined with dynamic voltage and frequency scaling (DVFS), power gating can be used very effectively to improve the overall power efficiency of a chip design. However, to achieve the design optimality, one has to carefully tradeoff between various supply noise components and the achievable power saving. Importantly, for DVFS applications that operate on multiple supply voltage levels, the design tradeoffs between supply noise and power saving can vary significantly across different operating points and hence must be carefully considered. We present a systematic design tradeoff analysis for power gating geared towards DVFS applications. We propose a multi-driver based scheme for driving sleep transistors and re-routable decap based design strategies for optimizing noise and power efficiency at different supply levels. Finally, we demonstrate an optimization-based automatic design flow that leads to about 30% leakage power saving.