A current source model (CSM) is presented for CMOS logic cells, which can be used for accurate analysis of delay in CMOS VLSI circuits. In current technology, CS model can be considered as an accurate model for modern static timing and noise analysis. By using the combinational CS model for CMOS logic cell, different values of parasitic capacitances are correctly evaluated. Output voltage waveform is designed by considering the logic cell as load. The output voltage of the CMOS inverter by using CS model is compared with HSPICE simulated output voltage waveform of an inverter. Analysis for output voltage waveform of CS model is accurate as near as approximately 98% to the HSPICE simulated waveform. By using the CS model, different parasitic capacitances are also being evaluated. Variations of these parasitic capacitances are also being evaluated for different values of input and output voltages.