Device- and System-Level Performance Modeling for Graphene P-N Junction Logic

Chenyun Pan and Azad Naeemi
Georgia Institute of Technology


Based on the property of angular dependent transmission probability of electron observed in graphene PN junction, a modified MUX-based graphene logic device is introduced. A more elaborate resistance model including ON resistance, leakage resistance and contact resistance is given as well as capacitance model of the device. Compared with CMOS technology, MUX-based logic graphene gate has lower output resistance, smaller device area and can perform XOR function more efficiently. Since interconnection plays an ever increasing role in digital circuit design, for the first time, module-level and system-level analysis are made for better evaluating the potential performance of graphene logic devices. Based on the analysis of a 32-bit Han-Carlson adder, module-level evaluation results indicate that MUX-based graphene logic circuits can outperform CMOS circuits in terms of both delay and power consumption. Both devices being evaluated are based on 15nm technology node. For the system-level analysis, the potential performance of graphene logic devices is evaluated using the device models given in this paper and the system-level models given in IntSim CAD tool, which shows that for the same power consumption and die size area, the graphene logic system can have 120% higher throughput than its Si CMOS counterpart.