24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits

Tadashi Yasufuku1,  Koji Hirairi2,  Yu Pu1,  Yun Fei Zheng1,  Ryo Takahashi1,  Masato Sasaki1,  Hiroshi Fuketa1,  Atsushi Muramatsu2,  Masahiro Nomura2,  Hirofumi Shinohara2,  Makoto Takamiya1,  Takayasu Sakurai1
1University of Tokyo, 2Semiconductor Technology Academic Research Center


A post-fabrication dual supply voltage (VDD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (VDDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average VDD below VDDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC’s circuit fabricated in 65nm CMOS. The layout of DES CODEC’s is divided into 64 VDD domains and each domain size is 54um x 63.2um. High VDD (VDDH) or low VDD (VDDL) is applied to each domain and the selection of VDD’s is performed based on multiple built-in self tests. VDDH is selected in VDDmin-critical domains, while VDDL is selected in VDDmin-non-critical domains. A maximum 24% power reduction was measured with the proposed PDVC at 300kHz, VDDH =437mV, and VDDL=397mV.