Functional Test Pattern Generation for Maximizing Temperature in 3D IC Chip Stack

Sudarshan Srinivasan and Sandip Kundu
Umass Amherst


In a stacked 3D Integrated Circuit (IC), the total power generated per unit surface area is extremely high. This result in creation of localized Hotspot’s in individual dies of 3D IC. The location and temperature of Hotspot depends on actual workloads applied to 3D IC. Since the workload applied to each of the dies in 3D IC keeps on changing continuously, generating temperature extremes is highly dependent on code sequence which would result in creation of localized hotspot regions in multiple dies of 3D IC. The workload applied can be classified as phases based on their execution profile and for each of the application, the spatial power dissipation pattern remains constant during a phase. Thus in this paper (i) we develop a wavelet-based temporal heat dissipation model for program traces, and use (ii) a novel Integer Linear Programming (ILP) formulation to generate synthetic test pattern to create worst case temperature. Experimental results show that by taking the spatio-temporal effect into account, we can raise temperature of a hotspot higher than what is possible otherwise. Hotspot temperature maximization is important in design verification and testing.