Timing errors act as a barrier to voltage scaling for digital logic. As the supply voltage decreases, transition times increase, leading to intersymbol interference between successive operations. We describe a novel technique that couples feedback equalization with a Schmitt trigger to suppress this interference, which in turn enables further voltage scaling. For a 4-bit, 22nm Kogge-Stone adder designed for a nominal voltage of 800mV, this technique lowers the critical voltage beyond which timing errors occur, providing a 20% decrease in energy per operation. We also apply this technique to a 3-tap finite impulse response filter, and observe that the energy per operation can be decreased by up to 40%.