Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices

Kaiyuan Yang1,  Dae Hyun Kim2,  Sung Kyu Lim2
1Tsinghua University, 2Georgia Institute of Technology


Three dimensional integrated circuits (3D ICs) with through-silicon vias (TSVs) potentially offer smaller footprint area, shorter wirelength, and better performance than 2D ICs. But, the 3D IC performance strongly depends on the TSV dimensions and parasitics. Using large TSVs may cause significant amount of silicon area overhead and weaken the benefit of wirelength reduction in 3D ICs. The non-negligible TSV parasitic capacitance can also result in delay overhead affecting the timing integrity. On the other hand, with the development of TSV manufacture, nano-scale TSVs are emerging, which is expected to reduce the overheads caused by using large TSVs. Therefore, this paper focuses on investigating the impact of nano-scale TSVs on the 3D IC performance at future technology nodes. We develop a 16nm standard cell library, compare the 3D IC designs with different process technologies (45nm, 22nm, and 16nm) and various TSVs diameters (from 5um to 100nm), and discuss the TSV impact on 3D ICs at each process node. The experimental results show that using nano-scale TSVs achieves significant improvements in footprint area, wirelength, and timing. Moreover, we propose a proper TSV dimension for each process node to develop high-performance 3D IC designs.