Thermal Via Structural Design in Three-Dimensional Integrated Circuits

Leslie Hwang,  Kevin Lin,  Martin Wong
University of Illinois


Vertical integration is a promising manufacturing technology to realize denser packaging and increased performance with reduced interconnect lengths for ``more than Moore''. However, thermal challenge is exacerbated on 3D integration implementations due to the low thermally conductive adhesive layer between device layers and denser packaging that causes increase power density. Thermal design on actual device layer needs to reduce the elevated heat generation of localized region with high power density, also known as hotspots, down to an operational range. One approach is to insert additional thermal TSVs that are electronically isolated with other parts of the chip, to act as vertical heat dissipating paths from each device layer to the heat sink. From previous research works, the TSV manufacturing process stresses surrounding features on the chip; therefore the number of TSVs needs to be minimized for maximum process reliability. We plan to design thermal structures that are easily manufacturable, less stressful to neighboring devices, more reliable and thermally effective. Furthermore, there is a high possibility to decrease the number of thermal TSVs inserted for similar or better heat dissipating effectiveness. The potential benefits may result in higher yield, performance and commercialization of 3D IC devices.